1. Field
Illustrative embodiments of the present disclosure relate to a semiconductor device performing a de-skew operation, and more particularly, to a semiconductor device including two circuits which transmit and receive data to and from each other and of which any one eliminates all skews during transmitting (Tx) and receiving (Rx) operations.
2. Description of the Related Art
FIGS. 1 to 3 are block diagrams respectively illustrating semiconductor devices 1, 2, and 3, each of which is configured to adjust a skew. A skew may arise between signals transmitted through different channels because of differences in signal propagation times of the different channels or variations in the properties of devices used to transmit and receive the signals.
In FIGS. 1 to 3, a data transmitting circuit indicates a data transmitting/receiving circuit operating in a transmission (Tx) mode, and a data receiving circuit indicates a data transmitting/receiving circuit operating in a reception (Rx) mode.
In the semiconductor device 1 of FIG. 1, the data transmitting circuit 10 transmits signals through channels 30 in synchronization with a global Tx clock signal GTCLK, and the data receiving circuit 20 receives the signals transmitted through the channels 30.
The data transmitting circuit 10 includes a Tx flip-flop 12 and a Tx buffer 13. The Tx flip-flop 12 latches data generated by a Tx core 11 in synchronization with the global Tx clock signal GTCLK.
The data receiving circuit 20 includes an Rx buffer 23 and a clock recovery circuit 24. The Rx buffer 23 receives a signal transmitted through any one line 31 of the channels 30, and the clock recovery circuit 24 generates a global Rx clock signal GRCLK from the signal outputted from the Rx buffer 23.
The data receiving circuit 20 includes a clock phase adjusting circuit 25 which generates a plurality of Rx clock signals by adjusting a phase of the global Rx clock signal GRCLK.
The data receiving circuit 20 includes an Rx flip-flop 22 and an Rx core 21. The Rx flip-flop 22 latches data in synchronization with an Rx clock signal outputted from the clock phase adjusting circuit 25, and the Rx core 21 receives the latched data from the Rx flip-flop 22.
In the semiconductor device 1 of FIG. 1, the clock phase adjusting circuit 25 within the data receiving circuit 20 provides the Rx clock signal with the adjusted phase to each channel, thereby eliminating a skew of the received data.
In the semiconductor device 2 of FIG. 2, the data receiving circuit 20A includes an Rx buffer 23 and a clock recovery circuit 24A. The Rx buffer 23 receives data from a reference channel 31 which is one of a plurality of channels, and the clock recovery circuit 24A generates a global Rx clock signal GRCLK from the data outputted from the Rx buffer 23.
The data receiving circuit 20A of FIG. 2 further includes a delay circuit 26 which adjusts a delay amount of data received through a corresponding channel of the other channels excluding the reference channel 31, based on a skew of the corresponding channel relative to the reference channel.
In the data receiving circuit 20A of FIG. 2, an Rx flip-flop 22A latches the data received through the reference channel 31 or the data outputted from the delay circuit 26 in synchronization with the global Rx clock signal GRCLK, and provides the latched data to the Rx core 21.
In the semiconductor devices 1 and 2 of FIGS. 1 and 2, the data receiving circuits 20 and 20A eliminates a skew of data. In FIG. 1, the data receiving circuit 20 eliminates a skew of data by adjusting the phase of the clock signal inputted to the Rx flip-flop 22. In FIG. 2, the data receiving circuit 20A eliminates a skew of data by adjusting the delay amount of data inputted to the Rx flip-flop 22A.
FIG. 3 illustrates the semiconductor device 3 in which a data transmitting circuit 10B eliminates a skew of data.
The data transmitting circuit 10B includes a clock phase adjusting circuit 15 which generates a plurality of Tx clock signals by adjusting a phase of a global Tx clock signal GTCLK according to phase information provided through a feedback channel 32 and a phase Rx buffer 14 from a data receiving circuit 20B.
A Tx flip-flop 12B latches data in synchronization with a corresponding Tx clock signal of the plurality of Tx clock signals.
The data receiving circuit 20B includes a phase comparison circuit 27 and a phase transmitting buffer 28. The phase comparison circuit 27 compares a phase of a global Rx clock signal GRCLK to phases of received data and outputs the phase information, and the phase transmitting buffer 28 receives the phase information and provides the received phase information to the feedback channel 32.
When the semiconductor devices 1 to 3 each includes a plurality of data receiving circuits, in the embodiments illustrated in FIGS. 1 and 2, each of the data receiving circuits includes the clock phase adjusting circuit 25 or the delay circuit 26 for the purpose of eliminating a skew of data in the data receiving circuit, thereby increasing the entire size of the semiconductor device. In the embodiment illustrated in FIG. 3, the phase comparison circuit 27 and the phase transmitting buffer 28 are added to each of the data receiving circuits 20B, and the feedback channel 32 is included in channels 30B.
FIG. 4 illustrates an example of a semiconductor device 4 which includes one data transmitting circuit 10 and a plurality of data receiving circuits 20. In FIG. 4, the semiconductor device 4 is a memory semiconductor device having a stacked structure in which one logic die 10C and a plurality of cell dies 20C are coupled through a plurality of through-electrodes 31C.
When the technologies of FIGS. 1 to 3 are applied to the semiconductor device 4, the same de-skew related circuits are included in each of the cell dies 20C. The area of the cell dies 20C used for cells is reduced as a result.
Furthermore, when the technologies of FIGS. 1 to 3 are applied to data transmitting/receiving circuits which perform two-way communication, a circuit for eliminating a data skew must be included in both of the data transmitting/receiving circuits. Thus, the area of the circuits may be further increased.